Existing systems and methods for processing digital video typically use separate and independent, fixed image processing blocks, such as for performing fixed de-interlacing, scaling, and other image processing functions. This results not only in increased redundancy and cost, it also potentially results in reduced image quality and processing efficiency. For example, where only pixel data is passed between the stages, processing enhancements achieved by a first stage may be counteracted by later processing by a second stage. For similar reasons, error magnification may occur, such as where processing by the second stage is not well-tuned to processing by the first stage. A further drawback is the sequential flow through the stages such that additional, targeted processing can not be performed. Sub-par image quality, high cost, and processing inefficiencies are problems that are faced in many digital video applications, including high definition television (HDTV). Still further, architectures in prior systems can result in large, multiple silicon implementations that increase cost and/or produce functional redundancies.